Conventional flash memory technology and related technologies are described in the following publications inter alia:
[1] Paulo Cappelletti, Clara Golla, Piero Olivo, Enrico Zanoni, “Flash Memories”, Kluwer Academic Publishers, 1999
[2] G. Campardo, R. Micheloni, D. Novosel, “VLSI-Design of Non-Volatile Memories”, Springer Berlin Heidelberg New York, 2005
[3] G. Proakis, “Digital Communications,” 3rd ed., New York: McGraw-Hill, 1995.
[4] “4-Bit-Per-Cell NROM Reliability”. Boaz Eitan, Guy Cohen, Assaf Shappir, Eli Lusky, Amichai Givant, Meir Janai, Ilan Bloom, Yan Polansky, Oleg Dadashev, Avi Lavan, Ran Sahar and Eduardo Maayan. Appears on the website of Saifun.com.
[5] Portal, J. M. et al. “EEPROM Diagnosis Based on Threshold Voltage Embedded Measurement”. Journal of Electronic Testing: Theory and Applications Volume 21, Issue 1 (January 2005)
[6] Himeno, T.; Matsukawa, N.; Hazama, H.; Sakui, K.; Oshikiri, M.; Masuda, K.; Kanda, K.; Itoh, Y.; Miyamoto, J. “A new technique for measuring threshold voltage distribution in flash EEPROM devices.” Microelectronic Test Structures, 1995. ICMTS 1995. Proceedings of the 1995 International Conference on Volume, Issue, 22-25 Mar. 1995 Page(s):283-287 Digital Object Identifier 10.1109/ICMTS.1995.513988
[7] G. Tao, A. Scarpa, J. Dijkstra, W. Stidl and F. Kuper, “Data retention prediction for modern floating gate non-volatile memories”, Microelectronics Reliability, Volume 40, Issues 8-10, August-October 2000, Pages 1561-1566
[8] Esseni, D., “Trading-off programming speed and current absorption in flash memories with the ramped-gate programming technique”, IEEE Transactions on Electron Devices, 47(4), April 2000.
[9] Portal, J. M. “EEPROM Memory: Threshold voltage built in self diagnosis”, ITC International Test Conference, Paper 2.1.
The disclosures of all publications and patent documents mentioned in the specification, and of the publications and patent documents cited therein directly or indirectly, are hereby incorporated by reference.